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Description: TLV1544与TMS320VC5402通过串行口连接，此时，A／D转换芯片作为从设备，DSP提供帧同步和输入／输出时钟信号。TLV1544与DSP之间数据交换的时序图如图3所示。
开始时， 为高电平（芯片处于非激活状态），DATA IN和I/OCLK无效，DATAOUT处于高阻状态。当串行接口使CS变低（激活），芯片开始工作，I／OCLK和DATAIN能使DATA OUT不再处于高阻状态。DSP通过I／OCLK引脚提供输入／输出时钟8序列，当由DSP提供的帧同步脉冲到来后，芯片从DATA IN接收4 b通道选择地址，同时从DATAOUT送出的前一次转换的结果，由DSP串行接收。I／OCLK接收DSP送出的输入序列长度为10～16个时钟周期。前4个有效时钟周期，将从DATAIN输入的4 b输入数据装载到输入数据寄存器，选择所需的模拟通道。接下来的6个时钟周期提供模拟输入采样的控制时间。模拟输入的采样在前10个I／O时钟序列后停止。第10个时钟沿（确切的I／O时钟边缘，即上升沿或下降沿，取决于操作的模式选择）将EOC变低，转换开始。
-TLV1544 with TMS320VC5402 through serial port connectivity, at this time, A / D conversion chip as from the equipment, to provide frame synchronization DSP and input / output clock signal. TLV1544 DSP and data exchange between the chronology of the map is shown in figure 3. At the beginning of the margin (in chip-activated), and I DATA IN / OCLK invalid, DATAOUT at high resistance state. When the serial interface CS change low (activator), the chip start work, I / OCLK and DATAIN can DATA OUT is no longer in a state of high resistance. DSP through I / OCLK pin provide input / output clock 8 sequence, When the DSP from the frame synchronization pulse, the chip from the DATA IN receive four channels to choose b address, DATAOUT sent from the same time the previous conversion results from the
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Size: 1207 |
Author: john |
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Description: TMS320VC5402 SPI DMA的开发例程,大家可以-TMS320VC5402 SPI DMA development routines, we can s
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Size: 2048 |
Author: 大好 |
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Description: EADSP5402DEMO的所有资料，包含原理图、代码、升级代码等。做MCU-HPI必备资料！-EADSP5402DEMO all the information, including drawings, code, promotion codes. Do MCU-HPI essential information!
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Size: 1640448 |
Author: 烦不烦阿 |
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Description: TLV1544与TMS320VC5402通过串行口连接，此时，A／D转换芯片作为从设备，DSP提供帧同步和输入／输出时钟信号。TLV1544与DSP之间数据交换的时序图如图3所示。
开始时， 为高电平（芯片处于非激活状态），DATA IN和I/OCLK无效，DATAOUT处于高阻状态。当串行接口使CS变低（激活），芯片开始工作，I／OCLK和DATAIN能使DATA OUT不再处于高阻状态。DSP通过I／OCLK引脚提供输入／输出时钟8序列，当由DSP提供的帧同步脉冲到来后，芯片从DATA IN接收4 b通道选择地址，同时从DATAOUT送出的前一次转换的结果，由DSP串行接收。I／OCLK接收DSP送出的输入序列长度为10～16个时钟周期。前4个有效时钟周期，将从DATAIN输入的4 b输入数据装载到输入数据寄存器，选择所需的模拟通道。接下来的6个时钟周期提供模拟输入采样的控制时间。模拟输入的采样在前10个I／O时钟序列后停止。第10个时钟沿（确切的I／O时钟边缘，即上升沿或下降沿，取决于操作的模式选择）将EOC变低，转换开始。
-TLV1544 with TMS320VC5402 through serial port connectivity, at this time, A/D conversion chip as from the equipment, to provide frame synchronization DSP and input/output clock signal. TLV1544 DSP and data exchange between the chronology of the map is shown in figure 3. At the beginning of the margin (in chip-activated), and I DATA IN/OCLK invalid, DATAOUT at high resistance state. When the serial interface CS change low (activator), the chip start work, I/OCLK and DATAIN can DATA OUT is no longer in a state of high resistance. DSP through I/OCLK pin provide input/output clock 8 sequence, When the DSP from the frame synchronization pulse, the chip from the DATA IN receive four channels to choose b address, DATAOUT sent from the same time the previous conversion results from the
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Size: 1024 |
Author: |
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Description: TMS320VC5402的中断程序和AIC23的音频输出解码程序,还有DSP的HPI自举程序.-TMS320VC5402 interrupt procedures and AIC23 audio output decoding process, as well as DSP
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Size: 140288 |
Author: 平凡 |
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Description: 摘 要:本文介绍了采用双声道音频A/D转换芯片CS5331A和TMS320VC5402 DSP组成的双声道音频采集系统
的设计。给出了系统的硬件设计方案,包括CS5331A与TMD320VC5402 DSP的接口电路和信号时序。在硬件方案
的基础上,给出了系统的总体软件流程,并详细介绍了DSP的多通道缓冲串行口(McBSP)和直接存储器访问(DMA)
的初始化设置,给出了相应例程。最后,给出了采集到DSP内存中的双声道音频数据的波形。
关键词:采集 DMA McBSP DSP
-Abstract: This paper describes the use of two-channel audio A/D conversion and TMS320VC5402 DSP chip CS5331A composed of two-channel audio acquisition system. Shows the system hardware design, including the CS5331A and TMD320VC5402 DSP interface circuit and signal timing. In the hardware solution, based on the given system' s overall software process, and details of the DSP multi-channel buffered serial port (McBSP) and direct memory access (DMA) initialization settings, gives the corresponding routines . Finally, given the collection to the DSP memory in two-channel audio data waveform. Keywords: acquisition DMA McBSP DSP
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Size: 188416 |
Author: ws |
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